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general description the max127/max128 are multirange, 12-bit data acquisi - tion systems (das) that require only a single +5v supply for operation, yet accept signals at their analog inputs that may span above the power-supply rail and below ground. these systems provide eight analog input chan - nels that are independently software programmable for a variety of ranges: 10v, 5v, 0 to +10v, 0 to +5v for the max127; and v ref , v ref /2, 0 to +v ref , 0 to +v ref /2 for the max128. this range switching increases the effective dynamic range to 14 bits and provides the flexibility to interface 4C20ma, 12v, and 15v-powered sensors directly to a single +5v system. in addition, these converters are fault protected to 16.5v; a fault condition on any channel will not affect the conversion result of the selected channel. other features include a 5mhz band - width track/hold, an 8ksps throughput rate, and the option of an internal 4.096v or external reference. the max127/max128 feature a 2-wire, i 2 c-compatible serial interface that allows communication among multiple devices using sda and scl lines. a hardware shutdown input ( shdn ) and two softwarepro - grammable power-down modes (standby and full power- down) are provided for low-current shutdown between conversions. in standby mode, the reference buffer remains active, eliminating startup delays. the max127/max128 are available in 24-pin narrow pdip or space-saving 28-pin ssop packages. applications industrial control systems data-acquisition systems robotics automatic testing battery-powered instruments medical instruments features 12-bit resolution, 1/2 lsb linearity +5v single-supply operation i 2 c-compatible, 2-wire serial interface four software-selectable input ranges ? max127: 0 to +10v, 0 to +5v, 10v, 5v ? max128: 0 to +v ref , 0 to +v ref /2, v ref , v ref /2 8 analog input channels 8ksps sampling rate 16.5v overvoltage-tolerant input multiplexer internal 4.096v or external reference two power-down modes 24-pin narrow pdip or 28-pin ssop packages pin configurations appear at end of data sheet. ordering information continued at end of data sheet.19-4773; rev 1; 12/12 +denotes a lead(pb)-free/rohs-compliant package. part temp range pin-package inl (lsb) max127 acng+ 0c to +70c 24 narrow pdip 1/2 max127acng+ 0c to +70c 24 narrow pdip 1 v dd ch0ch1 ch2 ch3 ch4 ch5 ch6 ch7 dgnd c 4.7f 0.1f 1k ? shdn +5v scl sda a0a1 a2 refrefadj agnd scl sda max127max128 analog inputs 0.01f max127/max128 multirange, +5v, 12-bit das with 2-wire serial interface typical operating circuit ordering information evaluation kit available downloaded from: http:///
v dd to agnd .......................................................... -0.3v to +6v agnd to dgnd ................................................... -0.3v to +0.3v ch0Cch7 to agnd .......................................................... 16.5v ref to agnd ........................................... -0.3v to (v dd + 0.3v) refadj to agnd .................................... -0.3v to (v dd + 0.3v) a0, a1, a2 to dgnd ................................. -0.3v to (v dd + 0.3v) shdn , scl, sda to dgnd .................................... -0.3v to +6v max current into any pin ................................................... 50ma continuous power dissipation (t a = +70c) 24-pin narrow pdip (derate 13.33mw/c above +70c) .......................... 1067mw 28-pin ssop (derate 15mw/c above +70c) ......... 1201mw operating temperature ranges max127_ c_ _/max128_ c_ _ .......................... 0c to +70c max127_ e_ _/max128_ e_ _ ...................... -40c to +85c storage temperature range ............................-65c to +150c lead temperature (soldering, 10s) ................................. +300c soldering temperature (reflow) ....................................... +260c (v dd = +5v 5%; unipolar/bipolar range; external reference mode, v ref = 4.096v; 4.7f at ref; external clock, f clk = 400khz; t a = t min to t max , unless otherwise noted. typical values are at t a = +25c.) parameter symbol conditions min typ max units accuracy (note 1) resolution 12 bits integral nonlinearity inl max127a 1/2 lsb max127b/max128b 1 differential nonlinearity dnl 1 lsb offset error unipolar max127a 3 lsb max127b/max128b 5 bipolar max127a 5 max127b/max128b 10 channel-to-channel offset error matching unipolar 0.1 lsb bipolar 0.3 gain error (note 2) unipolar max127a 7 lsb max127b/max128b 10 bipolar max127a 7 max127b/max128b 10 gain tempco (note 2) unipolar 3 ppm/c bipolar 5 dynamic specifications (800hz sine-wave input, 10v p-p (max127) or 4.096v p-p (max128), f sample = 8ksps) signal-to-noise plus distortion ratio sinad 70 db total harmonic distortion thd up to the 5th harmonic -87 -80 db spurious-free dynamic range sfdr 81 db channel-to-channel crosstalk 4khz, v in = 5v (note 3) -86 db dc, v in = 16.5v -96 aperture delay 200 ns aperture jitter 10 ns max127/max128 multirange, +5v, 12-bit das with 2-wire serial interface www.maximintegrated.com maxim integrated 2 absolute maximum ratings stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. electrical characteristics downloaded from: http:///
(v dd = +5v 5%; unipolar/bipolar range; external reference mode, v ref = 4.096v; 4.7f at ref; external clock, f clk = 400khz; t a = t min to t max , unless otherwise noted. typical values are at t a = +25c.) parameter symbol conditions min typ max units analog input track/hold acquisition time 3 s small-signal bandwidth -3db rolloff 10v or v ref range 5 mhz 5v or v ref /2 range 2.5 0 to 10v or 0 to v ref range 2.5 0 to 5v or 0 to v ref /2 range 1.25 input voltage range v in unipolar, table 3 max127 0 10 v 0 5 max128 0 v ref 0 v ref /2 bipolar, table 3 max127 -10 +10 -5 +5 max128 -v ref v ref -v ref /2 v ref /2 input current i in unipolar max127 0 to 10v range -10 +720 a 0 to 5v range -10 +360 max128 -10 +0.1 +10 bipolar max127 10v range -1200 +720 5v range -600 +360 max128 v ref range -1200 +10 v ref /2 range -600 +10 input resistance v in /i in unipolar 21 k? bipolar 16 input capacitance (note 4) 40 pf internal reference refout voltage v ref t a = +25c 4.076 4.096 4.116 v refout tempco tc v ref max127_c/max128_c 15 ppm/c max127_e/max128_e 30 output short-circuit current 30 ma load regulation (note 5) 0 to 0.5ma output current 10 mv capacitive bypass at ref 4.7 f refadj output voltage 2.465 2.500 2.535 v refadj adjustment range figure 12 1.5 % buffer voltage gain 1.638 v/v max127/max128 multirange, +5v, 12-bit das with 2-wire serial interface www.maximintegrated.com maxim integrated 3 electrical characteristics (continued) downloaded from: http:///
(v dd = +5v 5%; unipolar/bipolar range; external reference mode, v ref = 4.096v; 4.7f at ref; external clock, f clk = 400khz; t a = t min to t max , unless otherwise noted. typical values are at t a = +25c.) parameter symbol conditions min typ max units reference input (buffer disabled, reference input applied to ref) input voltage range 2.4 4.18 v input current v ref = 4.18v normal, or standby power-down mode 400 a full power-down mode 1 input resistance normal or standby power-down mode 10 k? full power-down mode 5 m? refadj threshold for buffer disable v dd - 0.5 v power requirements supply voltage v dd 4.75 5.25 v supply current i dd normal mode, bipolar ranges 18 ma normal mode, unipolar ranges 6 10 standby power-down mode (note 6) 700 850 a full power-down mode 120 220 power-supply rejection ratio (note 7) psrr external reference = 4.096v 0.1 0.5 lsb internal reference 0.5 timing external clock frequency range f clk 0.4 mhz conversion time t conv 6.0 7.7 10.0 s throughput rate 8 ksps bandgap reference startup time power-up (note 8) 200 s reference buffer settling time to 0.1mv, ref bypass capacitor fully discharged c ref = 4.7f 8 ms c ref = 33f 60 digital inputs ( shdn , a2, a1, a0) input high threshold voltage v ih 2.4 v input low threshold voltage v il 0.8 v input leakage current i in v in = 0v or v dd 0.1 10 a input capacitance c in (note 4) 15 pf input hysteresis v hys 0.2 v max127/max128 multirange, +5v, 12-bit das with 2-wire serial interface www.maximintegrated.com maxim integrated 4 electrical characteristics (continued) downloaded from: http:///
(v dd = +5v 5%; unipolar/bipolar range; external reference mode, v ref = 4.096v; 4.7f at ref; external clock, f clk = 400khz; t a = t min to t max , unless otherwise noted. typical values are at t a = +25c.) (v dd = +4.75v to +5.25v; unipolar/bipolar range; external reference mode, v ref = 4.096v; 4.7f at ref pin; t a = t min to t max , unless otherwise noted. typical values are at t a = +25c.) parameter symbol conditions min typ max units digital inputs (sda, scl) input high threshold voltage v ih 0.7 x v dd v input low threshold voltage v il 0.3 x v dd v input hysteresis v hys 0.05 x v dd v input leakage current i in v in = 0v or v dd 0.1 10 a input capacitance c in (note 4) 15 pf digital outputs (sda) output low voltage v ol i sink = 3ma 0.4 v i sink = 6ma 0.6 three-state output capacitance c out (note 4) 15 pf parameter symbol conditions min typ max units 2-wire fast mode scl clock frequency f scl 400 khz bus free time between a stop and start condition t buf 1.3 s hold time (repeated) start condition t hd,sta 0.6 s low period of the scl clock t low 1.3 s high period of the scl clock t high 0.6 s setup time for a repeated start condition t su,sta 0.6 s data hold time t hd,dat 0 0.9 s data setup time t su,dat 100 ns rise time for both sda and scl signals (receiving) t r c b = total capacitance of one bus line in pf 20 + 0.1 x c b 300 ns fall time for both sda and scl signals (receiving) t f c b = total capacitance of one bus line in pf 20 + 0.1 x c b 300 ns fall time for both sda and scl signals (transmitting) t f c b = total capacitance of one bus line in pf 20 + 0.1 x cb 250 ns set-up time for stop condition t su,sto 0.6 s capacitive load for each bus line c b 400 pf pulse width of spike suppressed t sp 0 50 ns max127/max128 multirange, +5v, 12-bit das with 2-wire serial interface www.maximintegrated.com maxim integrated 5 electrical characteristics (continued) timing characteristics downloaded from: http:///
note 1: accuracy specifications tested at v dd = 5.0v. performance at power-supply tolerance limits is guaranteed by power-supply rejection test. note 2: external reference: v ref = 4.096v, offset error nulled, ideal last-code transition = fs - 3/2 lsb. note 3: ground on channel, sine wave applied to all off channels. note 4: guaranteed by design. not tested. note 5: use static external load during conversion for specified accuracy. note 6: tested using internal reference. note 7: psrr measured at full scale. tested for the 10v (max127) and 4.096v (max128) input ranges. note 8: not subject to production testing. provided for design guidance only. (v dd = +4.75v to +5.25v; unipolar/bipolar range; external reference mode, v ref = 4.096v; 4.7f at ref pin; t a = t min to t max , unless otherwise noted. typical values are at t a = +25c.) parameter symbol conditions min typ max units 2-wire standard mode scl clock frequency f scl 100 khz bus free time between a stop and start condition t buf 4.7 s hold time (repeated) start condition t hd,sta 4.0 s low period of the scl clock t low 4.7 s high period of the scl clock t high 4.0 s setup time for a repeated start condition t su, sta 4.7 s data hold time t hd, dat 0 0.9 s data setup time t su, dat 250 ns rise time for both sda and scl signals (receiving) t r 1000 ns fall time for both sda and scl signals (receiving) t f 300 ns fall time for both sda and scl signals (transmitting) t f c b = total capacitance of one bus line in pf, up to 6ma sink 20 + 0.1 x c b 250 ns setup time for stop condition t su, sto 4.0 s capacitive load for each bus line c b 400 pf pulse width of spike suppressed t sp 0 50 ns max127/max128 multirange, +5v, 12-bit das with 2-wire serial interface www.maximintegrated.com maxim integrated 6 timing characteristics (continued) downloaded from: http:///
(v dd = +5v, external reference mode, v ref = 4.096v; 4.7f at ref; external clock, f clk = 400khz; t a = +25c, unless otherwise noted.) 0 5 1510 20 25 0 2 1 3 4 5 6 7 supply current vs. supply voltage max127/8-01 supply voltage (v) supply current (ma) 50 70 110 90 130 150 -40 10 -15 35 60 85 full power-down supply current vs. temperature max127/8-04 temperature (c) full power-down supply current (a) internalreference externalreference 0.1 0.2 0.60.5 0.4 0.3 0.7 0.8 -40 10 -15 35 60 85 channel-to-channel gain-error matching vs. temperature max127/8-07 temperature (c) channel-to-channel gain-error matching (lsb) bipolar mode unipolar mode 5.5 5.7 6.15.9 6.3 6.5 -40 10 -15 35 60 85 supply current vs. temperature max127/8-02 temperature (c) supply current (ma) 0.996 0.997 0.9990.998 1.000 1.001 -40 10 -15 35 60 85 normalized reference voltage vs. temperature max127/8-05 temperature (c) normalized reference voltage -0.15 -0.10 0.05 0 -0.05 0.10 0.15 0 1638 819 2457 3276 4095 integral nonlinearity vs. digital code max127/8-08 digital code integral nonlinearity (lsb) 50 150 450350 250 650550 750 -40 10 -15 35 60 85 standby supply current vs. temperature max127/8-03 temperature (c) standby supply current (a) internalreference externalreference 0 0.05 0.250.20 0.15 0.10 0.30 0.35 -40 10 -15 35 60 85 channel-to-channel offset-error matching vs. temperature max127/8-06 temperature (c) channel-to-channel offset-error matching (lsb) bipolar mode unipolar mode -110 -100 -40-60 -80 -20 0 0 1600 800 2400 3200 4000 fft plot max127/8-09 frequency (hz) amplitude (db) v dd = 5v f in = 800hz f sample = 8khz max127/max128 multirange, +5v, 12-bit das with 2-wire serial interface maxim integrated 7 www.maximintegrated.com typical operating characteristics downloaded from: http:///
pin name function narrow pdip ssop 1, 2 1, 2 v dd +5v supply. bypass with a 0.1f capacitor to agnd. 3, 9, 22, 24 4, 7, 8, 11, 22, 24, 25, 28 n.c. no connection. no internal connection. 4 3 dgnd digital ground 5 5 scl serial clock input 6, 8, 10 6, 10, 12 a0, a2, a1 address select inputs 7 9 sda open-drain serial data i/o. input data is clocked in on the rising edge of scl, and output data is clocked out on the falling edge of scl. external pullup resistor required. 11 13 shdn shutdown input. when low, device is in full power-down (fullpd) mode. connect high for normal operation. 12 14 agnd analog ground 13C20 15C21, 23 ch0Cch7 analog input channels 21 26 refadj bandgap voltage-reference output/external adjust pin. bypass with a 0.01f capacitor to agnd. connect to v dd when using an external reference at ref. 23 27 ref reference buffer output/adc reference input. in internal reference mode, the reference buffer provides a 4.096v nominal output, externally adjustable at refadj. in external reference mode, disable the internal reference by pulling refadj to v dd and applying the external reference to ref. max127/max128 multirange, +5v, 12-bit das with 2-wire serial interface www.maximintegrated.com maxim integrated 8 pin description downloaded from: http:///
detailed description converter operation the max127/max128 multirange, fault-tolerant adcs use successive approximation and internal track/hold (t/h) cir - cuitry to convert an analog signal to a 12-bit digital output. figure 1 shows the block diagram for these devices. analog-input track/hold the t/h circuitry enters its tracking/acquisition mode on the falling edge of the sixth clock in the 8-bit input control word and enters its hold/conversion mode when the mas - ter issues a stop condition. for timing information, see the start a conversion section. input range and protection the max127/max128 have software-selectable input ranges. each analog input channel can be independently programmed to one of four ranges by setting the appro - priate control bits (rng, bip) in the control byte (table 1). the max127 has selectable input ranges extending to 10v (v ref x 2.441), while the max128 has select - able input ranges extending to v ref . note that when an external reference is applied at refadj, the voltage at ref is given by v ref = 1.638 x v refadj (2.4 < v ref < 4.18). figure 2 shows the equivalent input circuit. a resistor network on each analog input provides a 16.5v fault protection for all channels. this circuit limits the current going into or out of the pin to less than 1.2ma, whether or not the channel is on. this provides an added layer of protection when momentary overvoltages occur at the selected input channel, and when a negative signal is applied at the input even though the device may be con - figured for unipolar mode. overvoltage protection is active even if the device is in power-down mode or v dd = 0v. digital interfacethe max127/max128 feature a 2-wire serial interface consisting of the sda and scl pins. sda is the data i/o and scl is the serial clock input, controlled by the master device. a2Ca0 are used to program the max127/max128 to different slave addresses. (the max127/max128 only work as slaves.) the two bus lines (sda and scl) must be high when the bus is not in use. external pullup resistors (1k? or greater) are required on sda and scl to maintain i 2 c compatibility. table 1 shows the input control-byte format. figure 1. block diagram figure 2. equivalent input circuit ch2 ch1 ch0 shdn ch3 ch4 ch5 ch6 ch7 refadj ref v dd agnddgnd 12-bit sar adc in ref clock out t/h 2.5v reference analog input mux and signal conditioning a v = 1.638 int clock sda a2 a1 a0 scl serial interface logic 10 k ? max127max128 5.12k ? r2 r1 ch_ s1s2 s3 s4 bipolar unipolar voltagereference t/hout hold track track hold off on c hold s1 = bipolar/unipolar switchs2 = input mux switch s3, s4 = t/h switch r1 = 12.5k ? (max127) or 5.12k ? (max128) r2 = 8.67k ? (max127) or (max128) max127/max128 multirange, +5v, 12-bit das with 2-wire serial interface www.maximintegrated.com maxim integrated 9 downloaded from: http:///
table 1. control-byte format table 3. range and polarity selection table 2. channel selection table 4. power-down and clock selection bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 start sel2 sel1 sel0 rng bip pd1 pd0 bit name description 7 (msb) start the logic 1 received after acknowledge of a write bit (r/ w = 0) deines the beginning of the control byte. 6, 5, 4 sel2, sel1, sel0 these three bits select the desired on channel (table 2) . 3 rng selects the full-scale input voltage range (table 3) . 2 bip selects unipolar or bipolar conversion mode (table 3) . 1, 0 (lsb) pd1, pd0 these two bits select the power-down modes (table 4) . sel2 sel1 sel0 channel 0 0 0 ch0 0 0 1 ch1 0 1 0 ch2 0 1 1 ch3 1 0 0 ch4 1 0 1 ch5 1 1 0 ch6 1 1 1 ch7 pd1 pd0 sel0 0 x normal operation (always on) 1 0 standby power-down mode (stbypd) 1 1 full power-down mode (fullpd) input range (v) rng bip negative full scale (v) zero scale (v) full scale (v) max127 0 to 5 0 0 0 v ref x 1.2207 0 to 10 1 0 0 v ref x 2.4414 5 0 1 -v ref x 1.2207 0 v ref x 1.2207 10 1 1 -v ref x 2.4414 0 v ref x 2.4414 max128 0 to v ref /2 0 0 0 v ref /2 0 to v ref 1 0 0 v ref v ref /2 0 1 -v ref /2 0 v ref /2 v ref 1 1 -v ref 0 v ref max127/max128 multirange, +5v, 12-bit das with 2-wire serial interface www.maximintegrated.com maxim integrated 10 downloaded from: http:///
slave address the max127/max128 have a 7-bit-long slave address. the first four bits (msbs) of the slave address have been factory programmed and are always 0101. the logic state of the address input pins (a2Ca0) determine the three lsbs of the device address (figure 3). a maximum of eight max127/max128 devices can therefore be con - nected on the same bus at one time.a2Ca0 may be connected to v dd or dgnd, or they may be actively driven by ttl or cmos logic levels. the eighth bit of the address byte determines whether the master is writing to or reading from the max127/max128 (r/ w = 0 selects a write condition. r/ w = 1 selects a read condition). conversion control the master signals the beginning of a transmission with a start condition (s), which is a high-to-low transition on sda while scl is high. when the master has finished communicating with the slave, the master issues a stop condition (p), which is a low-to-high transition on sda while scl is high (figure 4). the bus is then free for another transmission. figure 5 shows the timing diagram for signals on the 2-wire interface. the address-byte, control-byte, and data-byte are transmitted between the start and stop conditions. the sda state is allowed to change only while scl is low, except for the start and stop conditions. data is transmitted in 8-bit words. nine clock cycles are required to transfer the data in or out of the max127/max128. (figures 9 and 10). figure 3. address byte figure 5. 2-wire serial-interface timing diagram figure 4. start and stop conditions scl sda slave address bits a2, a1, and a0 correspond to the logic state of the address input pins a2, a1, and a0. 0 0 1 a2 1 r/w a1 a0 lsb ack slave address scl sda start condition stop condition repeated start condition start condition t su,dat t hd , dat t hd , sta t low t r t f t high t su , sta t hd , sta t su , sto t buf scl sda start condition stop condition max127/max128 multirange, +5v, 12-bit das with 2-wire serial interface www.maximintegrated.com maxim integrated 11 downloaded from: http:///
start a conversion (write cycle) a conversion cycle begins with the master issuing a start condition followed by seven address bits (figure 3) and a write bit (r/ w = 0). once the eighth bit has been received and the address matches, the max127/max128 (the slave) issues an acknowledge by pulling sda low for one clock cycle (a = 0). the master then writes the input control byte to the slave (figure 8). after this byte of data, the slave issues another acknowledge, pulling sda low for one clock cycle. the master ends the write cycle by issuing a stop condition (figure 6). when the write bit is set (r/ w = 0), acquisition starts as soon as bit 2 (bip) of the input control-byte has been latched and ends when a stop condition has been issued. conversion starts immediately after acquisition. the max127/max128s internal conversion clock fre - quency is 1.56mhz, resulting in a typical conversion time of 7.7s. figure 9 shows a complete write cycle. read a conversion (read cycle) once a conversion starts, the master does not need to wait for the conversion to end before attempting to read the data from the slave. data access begins with the mas - ter issuing a start condition followed by a 7-bit address (figure 3) and a read bit (r/ w = 1). once the eighth bit has been received and the address matches, the slave issues an acknowledge by pulling low on sda for one clock cycle (a = 0) followed by the first byte of serial data (d11Cd4, msb first). after the first byte has been issued by the slave, it releases the bus for the master to issue an acknowledge (a = 0). after receiving the acknowledge, the slave issues the second byte (d3Cd0 and four zeros) followed by a not acknowledge ( a =1) from the master to indicate that the last data byte has been received. finally, the master issues a stop condition (p), ending the read cycle (figure 7). figure 6. write cyclefigure 7. read cycle figure 8. command byte figure 9. complete 2-wire serial write transmission master to slaveslave to master no. of bits s slave address w a control-byte a p 1 7 1 1 8 1 1 start condition write acknowledge acknowledge stop condition master to slaveslave to master no. of bits s slave address r a data-byte a 1 7 1 1 8 1 data-byte a p 8 1 1 start condition read not acknowledge acknowledge stop condition lsb msb sda scl start sel2 sel1 sel0 rng bip pd1 pd0 ack st ar t: fi rs t logic 1 received after ack nowledge of a write. ack: ackno wled g e b it. t h e ma x 127 /m ax 128 p ull sd a l o w dur i ng t he 9th c lo ck p ul se. start condition stop condition control byte slave address byte scl a/d state sda msb msb lsb lsb w 1 2 7 8 9 10 11 15 16 17 18 bip s 1 0 pd1 pd0 a a acquisition conversion max127/max128 multirange, +5v, 12-bit das with 2-wire serial interface www.maximintegrated.com maxim integrated 12 downloaded from: http:///
the max127/max128 ignore acknowledge and not- acknowledge conditions issued by the master during the read cycle. the device waits for the master to read the output data or waits until a stop condition is issued. figure 10 shows a complete read cycle. in unipolar input mode, the output is straight binary. for bipolar input mode, the output is twos complement. for output binary codes see the transfer function section. applications information power-on reset the max127/max128 power up in normal operating mode, waiting for a start condition followed by the appropriate slave address. the contents of the input and output data registers are cleared at power-up. internal or external reference the max127/max128 operate with either an internal or an external reference (figures 11aC11c). an external ref - erence is connected to either ref or to refadj. the refadj internal buffer gain is trimmed to 1.6384 to provide 4.096v at ref from a 2.5v reference. internal reference the internally trimmed 2.50v reference is amplified through the refadj buffer to provide 4.096v at ref. bypass ref with a 4.7f capacitor to agnd and bypass refadj with a 0.01f capacitor to agnd (figure 11a). the internal reference voltage is adjustable to 1.5% (65 lsbs) with the reference-adjust circuit of figure 12. external reference to use the ref input directly, disable the internal buffer by connecting refadj to v dd (figure 11b). using the refadj input eliminates the need to buffer the reference externally. when the reference is applied at refadj, bypass refadj with a 0.01f capacitor to agnd (figure 11c). at ref and refadj, the input impedance is a minimum of 10k? for dc currents. during conversions, an external reference at ref must be able to drive a 400a dc load, and must have an output impedance of 10? or less. if the reference has higher input impedance or is noisy, bypass ref with a 4.7f capacitor to agnd as close to the chip as possible. with an external reference voltage of less than 4.096v at ref or less than 2.5v at refadj, the increase in rms noise to the lsb value (full-scale voltage/4096) results in performance degradation and loss of effective bits. power-down mode to save power, put the converter into low-current shut - down mode between conversions. two programmable power-down modes are available, in addition to the hardware shutdown. select stbypd or fullpd by pro - gramming pd0 and pd1 in the input control byte (table 4). when software power-down is asserted, it becomes effective only after the end of conversion. in all power - down modes, the interface remains active and conversion results may be read. input overvoltage protection is active in all power-down modes. figure 10. complete 2-wire serial read transmission start condition stop condition lsb data byte msb data byte slave address byte msb msb msb lsb lsb lsb 0 1 1 2 7 8 9 10 11 17 18 19 22 23 26 27 r a d11 d4 a d3 d0 a filled with 4 zeros max127/max128 multirange, +5v, 12-bit das with 2-wire serial interface www.maximintegrated.com maxim integrated 13 downloaded from: http:///
to power-up from a software-initiated power-down, a start condition followed by the correct slave address must be received (with r/ w = 0). the max127/max128 power-up after receiving the next bit. for hardware-controlled power-down (fullpd), pull shdn low. when hardware shutdown is asserted, it becomes effective immediately and any conversion in progress is aborted. choosing power-down modes the bandgap reference and reference buffer remain active in stbypd mode, maintaining the voltage on the 4.7f capacitor at ref. this is a dc state that does not degrade after standby power-down of any duration. in fullpd mode, only the bandgap reference is active. connect a 33f capacitor between ref and agnd to maintain the reference voltage between conversions and to reduce transients when the buffer is enabled and dis - abled. throughput rates down to 1ksps can be achieved without allotting extra acquisition time for reference recov - ery prior to conversion. this allows conversion to begin immediately after power-down ends. if the discharge of the ref capacitor during fullpd exceeds the desired limits for accuracy (less than a fraction of an lsb), run a stbypd power-down cycle prior to starting conversions. take into account that the reference buffer recharges the bypass capacitor at an 80mv/ms slew rate, and add 50s for settling time. auto-shutdown selecting stbypd on every conversion automatically shuts the max127/max128 down after each conversion without requiring any start-up time on the next conversion. figure 11a. internal reference figure 12. reference-adjust circuit figure 11b. external reference, reference at ref ref 10k ? 2.5v refadj c ref 4.7f max127max128 a v = 1.638 0.01f ref v dd 10k ? 2.5v 4.096v refadj c ref 4.7f max127max128 a v = 1.638 ref 2.5v 2.5v refadj 10k ? c ref 4.7f max127max128 a v = 1.638 0.01f figure 11c. external reference, reference at refadj 100k ? 510k ? 24k ? refadj +5v max127max128 0.01f max127/max128 multirange, +5v, 12-bit das with 2-wire serial interface www.maximintegrated.com maxim integrated 14 downloaded from: http:///
transfer function output data coding for the max127/max128 is binary in unipolar mode with 1 lsb = (fs/4096) and twos complement binary in bipolar mode with 1 lsb = [(2 x |fs|)/4096]. code transitions occur halfway between successive-integer lsb values. figures 13a and 13b show the input/output (i/o) transfer functions for unipolar and bipolar operations, respectively. for full-scale (fs) values, refer to table 3. layout, grounding, and bypassing careful pcb layout is essential for best system perfor - mance. for best performance, use a ground plane. to reduce crosstalk and noise injection, keep analog and digital signals separate. connect analog grounds and dgnd in a star configuration to agnd. for noise-free operation, ensure the ground return from agnd to the supply ground is low impedance and as short as possible. connect the logic grounds directly to the supply ground. bypass v dd with 0.1f and 4.7f capacitors to agnd to minimize highand low-frequency fluctuations. if the supply is excessively noisy, connect a 5? resistor between the supply and v dd , as shown in figure 14. figure 13a. unipolar transfer function figure 13b. bipolar transfer function figure 14. power-supply grounding connection output code input voltage (lsb) 0 fs fs - 3 / 2 lsb 1 lsb = full-scale transition 1 2 3 11... 111 11... 110 11... 101 00... 01100... 010 00... 001 00... 000 fs 4096 output code input voltage (lsb) 0 +fs - 1 lsb 1 lsb = -fs 011... 111011... 110 000... 001 000... 000 111... 111 100... 010 100... 001 100... 000 2 fs 4096 v dd gnd dgnd dgnd agnd +5v +5v supply r* = 5 ? digital circuitry ** * optional** connect agnd and dgnd with a ground plane or a short trace. 0.1f 4.7f max127max128 max127/max128 multirange, +5v, 12-bit das with 2-wire serial interface www.maximintegrated.com maxim integrated 15 downloaded from: http:///
+denotes a lead(pb)-free/rohs-compliant package. part temp range pin-package inl (lsb) max127acai+ 0c to +70c 28 ssop 1/2 max127bcai+ 0c to +70c 28 ssop 1 max127aeng+ -40c to +85c 24 narrow pdip 1/2 max127beng+ -40c to +85c 24 narrow pdip 1 max127aeai+ -40c to +85c 28 ssop 1/2 max127beai+ -40c to +85c 28 ssop 1 max128bcng+ 0c to +70c 24 narrow pdip 1 max128bcai+ 0c to +70c 28 ssop 1 max128beng+ -40c to +85c 24 narrow pdip 1 max128beai+ -40c to +85c 28 ssop 1 package type package code outline no. land pattern no. 24 pdip n24+8 21-0043 28 ssop a28+3 21-0056 90-0095 2827 26 25 24 23 22 21 20 19 18 17 16 15 12 3 4 5 6 7 8 9 1011 12 13 14 n.c.ref refadj n.c. n.c. ch7 ch0 n.c.ch6 ch5 ch4 ch3 ch2 ch1 agnd shdn a1 n.c. a2 sda n.c. n.c. a0 scl n.c. dgnd v dd v dd ssop top view 2423 22 21 20 19 18 17 12 3 4 5 6 7 8 n.c.ref n.c. refadj dgnd n.c. v dd v dd ch7ch6 ch5 ch4 a2 sda a0 scl 1615 14 13 9 1011 12 ch3ch2 ch1 ch0 agnd shdn a1 n.c. narrow pdip max127max128 + + max127max128 maxim integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim integrated product. no circuit patent licenses are implied. maxim integrated reserves the right to change the circuitry and speciications without n otice at any time. the parametric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidance. maxim integrated and the maxim integrated logo are trademarks of maxim integrated products, inc. max127/max128 multirange, +5v, 12-bit das with 2-wire serial interface ? 2012 maxim integrated products, inc. 16 package information for the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. chip information process: bicmos ordering information (continued)pin conigurations for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim integrateds website at www.maximintegrated.com. downloaded from: http:///

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